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M66313FP
32-Bit LED Driver with Shift Register and Latch
REJ03F0179-0201 Rev.2.01 Mar 31, 2008
Description
The M66313FP is a semiconductor integrated circuit for LED array driver with 32-bit serial-input, parallel-output shift register, equipped with direct set input and output latches. The M66313FP guarantees sufficient 24 mA output current to drive anode common LED, allowing 32-bit simultaneous and continuous current output. The parallel outputs are open-drain outputs. The M66313FP employs CMOS technology, allowing considerable reduction of power dissipation, compared to previous BIPOLAR or Bi-CMOS products. In addition, the pin configuration is suitable for easy wiring on the printed circuit board.
Features
* High output current. All parallel output IOL = +24 mA, LEDs can be turned on simultaneously. * Low power dissipation : 200 W/package (max) (VCC = 5 V, Ta = 25C, quiescent state) * High noise margin Employment of Schmitt-trigger circuit on all inputs allows application with long wiring. * Direct set input (SD) * Open-drain output (Q1 to Q32) * Serial data output for cascading (SQ32) * Wide operating temperature range (Ta = -40 to +85C) * Pin configuration for easy layout on PCB. (Pin configuration allows easy cascade connection or LED connection)
Application
LED array drive for eraser unit of a copying machine LED array drive of a button telephone set Various LED modules
REJ03F0179-0201 Rev.2.01 Mar 31, 2008 Page 1 of 9
M66313FP
Block Diagram
Parallel data outputs Q1
2
Serial data output Q30
18
Q2
3
Q3
4
Q4
5
Q29
17
Q31
19
Q32
20
SQ32
14
VCC
8
............... ......
0 LE D SD 0 LE D SD 0 LE D SD 0 LE D SD 0 LE D SD 0 LE D SD 0 LE D SD 0 D LE SD
...... ......
1 CK D SD 1 CK D SD 1 CK D SD 1 CK D SD
............ ...... ......
1 CK D SD
1 CK D SD
1 CK D SD
1 CK D SD
10
9
13
12
11
1
32
21
OE A Output Serial enable data input input
VCC
VCC
CK SD LE GND1 GND2 GND3 Shift Direct Latch clock set enable input input input SQ32
Q1 to Q32
Parallel output
Serial output
Output type
REJ03F0179-0201 Rev.2.01 Mar 31, 2008 Page 2 of 9
M66313FP
Pin Arrangement
M66313FP
GND1
1 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 A OE LE SD CK Q17 Q18 Q15 Q16 42 Q7 41 Q8 40 Q9 39 Q10 38 Q11 37 Q12 36 Q13 35 Q14 34 Q15 33 Q16 32 GND2 31 Q17 30 Q18 29 Q19 28 Q20 27 Q21 26 Q22 25 Q23 24 Q24 23 Q25 22 Q26
Q1 2 Q2 3 Parallel data outputs Q3 4 Q4 5 Q5 6 Q6 7 VCC Serial data input Output enable input Latch enable input Direct set input Shift clock input
8
Parallel data outputs
A 9 OE 10 LE 11 SD 12 CK 13 Q27 15 Q28 16 Q29 17 Q30 18 Q31 19 Q32 20 GND3 21
Serial data output SQ32 14
SQ32 Q19 Q27 Q28 Q29 Q30 Q31 Q32 Q20 Q21 Q22 Q23 Q24 Q25 Q26
Parallel data outputs
Parallel data outputs
(Top view) Outline: 42P2R-A
Functional Description
The employment of silicon gate CMOS process of the M66313FP guarantees low power dissipation and maintains high noise margin as well as high output current and high speed required to drive LEDs. Each shift register bit consists of a flip-flop for shifting and an output latch. The shift operation takes place when the clock input CK changes from low-level to high-level. The serial data input A corresponds to the data input of the first-stage shift register, and the shift register is shifted in sequence when a pulse is applied to CK. The parallel outputs Q1 to Q32 are open-drain outputs. If the latch-enable input LE is turned high-level, the content of the shift register at that instant is latched. To expand the number of bits, use the serial data output SQ32 which shows the output of the shift register of the 32nd bit. If the direct set input SD is turned low-level, shift register and latches are set. If the high-level input is applied to the output enable input OE, Q1 to Q32 are set to the high-impedance state, but SQ32 is not set to the high-impedance state. The shift operation is not affected when OE is changed.
REJ03F0179-0201 Rev.2.01 Mar 31, 2008 Page 3 of 9
M66313FP Function Table (Note)
Input L H H Latch Output disable H X X X X X L L H X X H L X X L L L H L L L L L L L L L L L L L Parallel Data Output L L L L L L L L L L L L L L L L L L L Serial Data Output SQ32 H
Operation Mode Set Shift
SD CK LE A OE Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q25 Q26 Q27 Q28 Q29 Q30 Q31 Q32
L Q01 Q02 Q03 Q04 Q05 Q06 Q07 Q08 Q09 Q010 Q011 Q012 Q013 Q014 Q015 Q016 Q017 Q018 Q019 Q020 Q021 Q022 Q023 Q024 Q025 Q026 Q027 Q028 Q029 Q030 Q031 q031 Z Q01 Q02 Q03 Q04 Q05 Q06 Q07 Q08 Q09 Q010 Q011 Q012 Q013 Q014 Q015 Q016 Q017 Q018 Q019 Q020 Q021 Q022 Q023 Q024 Q025 Q026 Q027 Q028 Q029 Q030 Q031 q031 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z q32
L Q01 Q02 Q03 Q04 Q05 Q06 Q07 Q08 Q09 Q010 Q011 Q012 Q013 Q014 Q015 Q016 Q017 Q018 Q019 Q020 Q021 Q022 Q023 Q024 Q025 Q026 Q027 Q028 Q029 Q030 Q031 Q032 q32
Note
: Transition from low-to-high-level. Q0: Shows the status of output Q before CK input changes. X: Irrelevant 0 q : The content of shift register before CK changes. q: The content of the shift register. Z: High-impedance state.
Absolute Maximum Ratings
(Ta = -40 to +85C, unless otherwise noted)
Item Supply voltage Input voltage Output voltage Input protection diode current Output parasitic diode current Output current Supply/GND current Power dissipation Storage temperature range Q1 to Q32 SQ32 Symbol VCC VI VO IIK IOK IO ICC Pd Tstg Ratings -0.5 to + 7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 -20 20 -20 20 50 25 -920, +20 650 -65 to +150 Unit V V V mA mA mA mA mW C VCC, GND Conditions
VI < 0 V VI > VCC VO < 0 V VO > VCC
Recommended Operating Conditions
Item Supply voltage Input voltage Output voltage Operating free-air ambient temperature range Symbol VCC VI VO Topr Min 4.5 0 0 -40 Limits Typ 5 -- -- -- Max 5.5 VCC VCC +85 Unit V V V C
REJ03F0179-0201 Rev.2.01 Mar 31, 2008 Page 4 of 9
M66313FP
Electrical Characteristics
(VCC = 4.5 to 5.5 V, unless otherwise noted)
Limits Ta = 25C Item Positive-going threshold voltage Negative-going threshold voltage High-level output voltage Low-level output voltage SQ32 Sym bol VT+ VT- VOH Typ Min 0.35xVCC 0.2xVCC VCC-0.1 3.83 Q1 to Q32 VOL -- -- -- SQ32 High-level input current Low-level input current Maximum output leak current Q1 to Q32 IIH IIL IO -- -- -- -- -- -- ICC --
(Note1)
Ta = -40 to +85C Max 0.7xVCC 0.55xVCC -- -- 0.1 0.41 0.48 0.1 0.44 0.5 -0.5 1.0 -1.0 40.0 Min 0.35xVCC 0.2xVCC VCC-0.1 3.66 -- -- -- -- -- -- -- -- -- -- Max 0.7xVCC 0.55xVCC -- -- 0.1 0.50 0.55
(Note 2)
Unit V V V
Conditions VO = 0.1V, VCC-0.1V IO = 20A VO = 0.1V,VCC-0.1V IO = 20A VI = VT+,VT- VCC = 4.5V IOH = -20A IOH = -4mA IOL = 20A IOL = 24mA IOL = 28mA IOL = 20A IOL = 4mA
2.8 2 -- -- -- 0.20 0.25 -- -- -- -- -- -- --
V
VI = VT+,VT- VCC = 4.5V
0.1 0.53 5.0 -5.0 10.0 -10.0 400.0 A A A A
VI = VCC, VCC = 5.5V VI = GND, VCC = 5.5V VI = VT+, VT- VCC = 5.5V VI = VCC, GND, VCC = 5.5V VO = VCC VO = GND
Quiescent state dissipation current
Note:
1. All typical values are at VCC = 5 V, Ta = 25C 2. Ta = -40 to +70C
REJ03F0179-0201 Rev.2.01 Mar 31, 2008 Page 5 of 9
M66313FP
Switching Characteristics
(VCC = 5V)
Limits Ta = 25C Typ 30 35 35 35 40 35 40 30 35 30 35 3 6 160 Ta = -40 to +85C Min Max 4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 200 250 130 130 200 130 130 200 130 200 10 15 --
Item Maximum clock frequency Output enable time to low-level Output disable time from low-level Low-to-high, high-tolow output propagation time Output enable time to low-level Low-to-high output propagation time Output enable time to low-level Output disable time from low-level Output enable time to low-level CK-Q1 to Q32 (Turned on) CK-Q1 to Q32 (Turned off) CK-SQ32
Symbol fmax tPZL tPLZ tPLH tPHL tPZL tPLH tPZL tPLZ tPZL tPLZ CI CO CPD
Min 5 -- -- -- -- -- -- -- -- -- -- -- -- --
Max -- 150 200 100 100 150 100 100 150 100 150 10 15 --
Unit MHz ns ns ns ns ns ns ns ns ns ns pF pF pF
Conditions CL = 50 pF RL = 1 k
(Note 2)
SD-Q1 to Q 32 (Turned on) SD-SQ32 LE- Q 1 to Q 32 (Turned on) LE-Q1 to Q32 (Turned off) OE-Q1 to Q32 (Turned on)
Output disable time OE-Q1 to Q32 from low-level (Turned off) Input capacitance Output capacitance Power dissipation capacitance (Note 1) Note
OE-VCC
1. CPD is the equivalent capacitance of IC calculated by the operating power dissipation without load. The operating power dissipation without load is given as follows. 2 PD = CPD * VCC * fI + ICC * VCC
REJ03F0179-0201 Rev.2.01 Mar 31, 2008 Page 6 of 9
M66313FP
Timing Requirements
(VCC = 5V)
Limits Item CK, LE, SD pulse width Setup time A to CK Hold time A to CK Hold time LE to CK Recovery time CK to SD Note: 2. Test Circuit
VCC Input VCC RL PG 50 GND DUT SQ32 CL Q1 to Q32 CL
Symbol tW tsu th trec
Min 100 100 10 50 50
Ta = 25C Typ 16 27 5 15 20
Max -- -- -- -- --
Ta = -40 to +85C Min Max 130 130 15 70 70 -- -- -- -- --
Unit ns ns ns ns
Conditions
(Note 2)
(1) Characteristics of pulse generator (PG): tr = 6 ns, tf = 6 ns (2) CL includes probe and stray capacitance.
REJ03F0179-0201 Rev.2.01 Mar 31, 2008 Page 7 of 9
M66313FP
Timing Chart
tw tw tw
VCC CK
50% tPLH 50% 50% tPHL 50% tPZL 50%
GND VOH VOL VCC
LE
50% 50% tPZL
VCC GND VCC
SQ32
50% tPLZ
Q1 to Q32 Q1 to Q32
50% tPLZ
VOL VCC
Q1 to Q32
10%
10%
VOL
VOL
tw
VCC SD
50% 50% trec
GND VCC
A
VCC
50% tsu th 50%
GND VCC
50%
CK
tPLH
50%
GND VOH
CK
GND
SQ32
50% tPZL
VOL VCC
Q1 to Q32
50%
VOL
th
LE
VCC
50%
GND VCC GND VCC
10%
OE
50% tPZL
50% tPLZ
CK
50%
VCC GND VCC VOL
Q1 to Q32
50%
VOL
Q1 to Q32
REJ03F0179-0201 Rev.2.01 Mar 31, 2008 Page 8 of 9
M66313FP
Package Dimensions
42P2R-A
EIAJ Package Code SSOP42-P-450-0.80
42
MMP
JEDEC Code -- Weight(g) 0.63
22
Plastic 42pin 450mil SSOP
Lead Material Alloy 42/Cu Alloy e b2
HE
E
e1
F
Recommended Mount Pad Dimension in Millimeters Min Nom Max -- -- 2.4 0.05 -- -- -- 2.0 -- 0.35 0.4 0.5 0.13 0.15 0.2 17.3 17.5 17.7 8.2 8.4 8.6 -- 0.8 -- 11.63 11.93 12.23 0.3 0.5 0.7 -- 1.765 -- -- 0.75 -- -- 0.9 -- -- -- 0.15 0 -- 10 -- 0.5 -- -- 11.43 -- -- 1.27 --
Symbol
1 21
A
G
D
A2 e y
b
A1
A A1 A2 b c D E e HE L L1 z Z1 y b2 e1 I2
L1
c z Z1 Detail G Detail F
REJ03F0179-0201 Rev.2.01 Mar 31, 2008 Page 9 of 9
L
I2
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